1. Field of the Invention
The invention relates generally to the field of semiconductor memories and more specifically to non-volatile electrically erasable and/or programmable memories (EPROMs, EEPROMs or Flash memories), and to a program for the generation of a high ramp voltage for the supply of a load, especially a high voltage for the programming or erasure of at least one memory cell. It can be applied especially to.
2. Discussion of Related Art
A memory cell of an EEPROM consists of a floating-gate transistor (FIG. 1) comprising a control gate 101, a floating gate 102, a source region 103, a drain region 104, an oxide layer 105 and a substrate region 106. The gate 102 is the storage element, it is said to be floating because it has no contact with the exterior imposing a potential on it. The control gate 101 is connected to a word line of the memory and the drain region 104 is connected to a bit line of the memory. The structure shown in FIG. 1 shows that the oxide thickness 105 between the floating gate 102 and the substrate region 106 is very small. Typically, it is in the range of some nanometers. The small oxide thickness enables electrons to pass at this place by tunnel effect.
For the programming or erasure of a memory cell of this kind, it is necessary to produce high voltages of the order of 15 to 20 volts. The terms "high voltage" or "strong voltage" are used hereinafter to designate a voltage, in the range of 15 to 20 volts, that is high as compared with the general supply voltage of the circuit which is in the range of 3 to 5 volts and which may even be lower, for example 1.8 volts.
To program a memory cell, a positive high voltage is applied to the bit line of the memory, connected to the control gate 101 of the memory cell, and a zero voltage is applied to the bit line connected to the drain region 104. The application of these voltages creates a high electrical field through the narrow oxide layer 105. The result of this is the migration of electrons to the floating gate 102 by tunnel effect. These electrons are then trapped in the floating gate 102.
Conversely, to erase the memory cell, a high positive voltage is applied to the bit line and a zero voltage is applied to the word line. The migration of the electrons then takes place in the reverse direction and the floating gate 102 gets discharged. Thus, the high programming or erasure voltage is transmitted to a programming input of the memory array which behaves like a load that is essentially capacitive owing to the parasitic capacitances of the floating-gate transistors that form it.
The high programming or erasure voltage may be produced by supply means external to the integrated circuit incorporating the memory. However, when the integrated circuit for which a high programming voltage has to be produced is a mounted circuit, in particular when it is a chip of a chip card, the high programming voltage must be produced within the integrated circuit itself from its general supply voltage. There is a known way of using a low general supply voltage, for example of 5 volts, to produce high internal voltages, for example in the range of 20 volts.
The development of technologies however is leading to recommendations for the use of general supply voltages with lower values, for example voltages of3 volts, or even 1.8 volts. The usefulness of these very low voltage solutions is that the total energy dissipated in an integrated circuit is reduced. Its temperature is therefore lower, and it works all the more efficiently. Furthermore, with the miniaturizing of the circuits, the breakdown voltages or the voltages corresponding to changes in state are reduced so that a low voltage supply becomes a necessity. However, despite this miniaturization, it is still necessary to have recourse to high programming voltages.
The principle of the production of a high voltage within an integrated circuit consists of the use of a voltage booster circuit within this integrated circuit. A voltage booster circuit comprises, for example, a SCHENKEL type multiplier or else, more conventionally, a load pump. The technique of the manufacture of these booster circuits is such that, for a given supply voltage equal for example to 5 volts, the value of the high voltage produced is limited to a maximum, for example 20 volts. If the supply voltage is lower, for example, 3 volts, it becomes impossible to produce potential differences above 18 volts, for example by producing positive voltages and negative voltages in the circuit. It will be understood that, owing to this technological development, it is becoming increasingly difficult to generate programming or erasure voltages with a value that is high enough to enable their function to be fulfilled. This is all the truer if the supply voltage is below 3 volts.
Furthermore, the greater the value of the high voltage produced as compared with the initial general supply voltage, the lower is the fan-out of the voltage booster, especially when this booster is a load pump.
It is known that the fan-out of the booster, among other things, determines the performance characteristics of the circuit in terms of the number of memory cells that can be programmed or erased at the same time, and in terms of speed. It is therefore necessary to achieve a compromise between, firstly, the value of the high voltage delivered by the booster circuit and, secondly, the fan-out of said circuit. Be that as it may, any drop in voltage allowed between the output of the booster circuit and the programming or erasure input of the memory array causes a limitation of the performance characteristics of the circuit. Indeed, to maintain a sufficient value of the high programming or erasure voltage, it is necessary to compensate for this drop in voltage by a voltage that is all the higher at output of the booster circuit, which therefore reduces its fan-out.
Furthermore, during the transfer of electrons between the floating gate 102 and the drain region 104 of the memory cell, it is indispensable that the variation of the electrical field created between the two zones should not be very sudden so as not to embrittle or even damage the oxide layer 105.
Consequently, a circuit is generally used for the generation of a high ramp voltage enabling a linear increase in the voltage applied to the control (programing) gate 101 or to the drain (erasure) region 104 of the memory cell. The slope of the ramp must be kept below a critical value above which the oxide layer of the floating-gate transistors would be damaged.
It is an object of the present invention is to propose a circuit for the generation of a high ramp voltage whose slope is well controlled and whose maximum value, (at the end of the ramp) is high enough while at the same time having good performance characteristics.
It is possible first of all to think of making the voltage delivered by the booster circuit itself vary linearly and in an increasing manner, for example by routing a large but decreasing quantity of the output current of the load pump towards the ground. In this way, the voltage at output of the booster circuit is prevented from reaching its nominal value (which determines the maximum value of the ramp) far too quickly, and it is thus possible to control the rise in voltage at output of the booster circuit in order to keep the slope of this voltage below the critical value. The output of the booster circuit may then be connected directly to the programming or erasure input of the memory array, so that no drop in voltage will be introduced between these two circuit points. The maximum end-of-ramp voltage may reach the nominal value of the high voltage delivered by the booster circuit. An approach of this kind nevertheless has a twofold drawback. Firstly, the load pump constituting the booster circuit delivers high current until its nominal output voltage has been built up, for it then has very low impedance. And forcing its output to remains below this nominal voltage therefore requires the routing of a high current towards the ground, which is done with a total loss. This is particularly detrimental in applications where the general supply is provided by a power source with limited load, such as a cell or a battery. Furthermore, the working of the load pump during the build-up of its nominal output voltage is a cause of disturbance, especially electromagnetic disturbance, likely to damage the efficiency of the memory. An approach of this kind is therefore not satisfactory.
It is therefore preferred according to the invention to design a circuit for the generation of a high ramp voltage of the type in which the high ramp voltage is generated from a high direct voltage with a constant value delivered by a booster circuit. The high ramp voltage is available at output of this generation circuit (and not directly at output of the booster circuit) which is connected to the place of application of the voltage ramp (i.e. to the programming or erasure input of the memory array).
There are known circuits of this kind in which an N type transistor is connected by its drain to the output of a booster circuit delivering a high direct voltage with a constant value and, by its source, to the load formed by the programming or erasure input of the memory array. To the gate of this N type transistor, there is applied a voltage that increases regularly with time so as to control the voltage available at the source. It can then be seen that, except for an intrinsic drop in voltage VTN, this voltage available at the source follows the value of the voltage applied to the control gate of this N type transistor. The load, connected to the source of the N type transistor, is therefore supplied with voltage.
In the prior art, an N type transistor of this kind connected as a load transistor is always used when, as is the case here, a high load current is likely to be delivered into the load. Indeed, all things being equal, the drain current of an N type transistor is higher than that of a P type transistor (because of a greater mobility of the load carrier).
However, the intrinsic voltage drop caused in the N type transistor is generally equal to 2 volts. This leads to a situation where it is no longer possible to have anything but a maximum end-of-ramp voltage of 16 volts with a constant high direct voltage, delivered by the voltage booster circuit, that is equal to 18 volts. If a voltage of over 16 volts is desired, the value of the high voltage delivered by the booster circuit must be increased to the detriment of the fan-out of the load pump, as stated here above.
In the application of the invention to the generation of a high voltage for the programming or erasure of a memory, the capacitive load is formed solely by all the connection nodes, the bit lines or the word lines, of the memory array.
Assuming that the value of the capacitive load is constant, it is enough to maintain a constant delivery of current to the P type load transistor so that the voltage at its drain is a voltage in a rising linear ramp with a constant slope determined by the ratio between the load current and the (constant) value of the capacitive load. For a specified programming or erasure operation, the value of the capacitive load may effectively be kept constant during the operation. However, in reality, it cannot be considered to be constant from one operation to another. Indeed, when the operation is, for example, a refresh programming operation, this value will depend on the initial state of the memory cell to be programmed. When it is an erasure operation, it will depend on the number of memory cells to be erased (for it is possible to erase only one cell, a group of cells or all the cells of the memory array).